This is a port map for the Super FX 2 chip used in Yoshi's Island SNES .
The SFX2 is a coprocessor for the SNES, in YI it is clocked at 21.4MHz, it is located inside the game cartridge.
The processor does not always run, it executes code untill it hits a STOP command.
The FX chip can render pseudo-3D graphics, rotate/scale GFX, apply lighting/shading to GFX, it also is used to decompress data, used to execute more complicated AI code, its CPU also has a multiplication oppcode which the SNES CPU does not have. The Yoshi's Island cartridge has an extra 16 pins on the side, however none are used.
ROMS are limited to 2MB in size, because the lack of extra address lines.
Port |
Size |
Type |
Name |
Info |
|---|---|---|---|---|
| 0x003000 | 2 | R/W | FX Register R0 | Default source/destination register |
| 0x003002 | 2 | R/W | FX Register R1 | Pixel plot X position register |
| 0x003004 | 2 | R/W | FX Register R2 | Pixel plot Y position register |
| 0x003006 | 2 | R/W | FX Register R3 | |
| 0x003008 | 2 | R/W | FX Register R4 | Lower 16 bit result of lmult |
| 0x00300A | 2 | R/W | FX Register R5 | |
| 0x00300C | 2 | R/W | FX Register R6 | Multiplier for fmult and lmult |
| 0x00300E | 2 | R/W | FX Register R7 | Fixed point texel X position for merge |
| 0x003010 | 2 | R/W | FX Register R8 | Fixed point texel Y position for merge |
| 0x003012 | 2 | R/W | FX Register R9 | |
| 0x003014 | 2 | R/W | FX Register R10 | |
| 0x003016 | 2 | R/W | FX Register R11 | Return address set by link |
| 0x003018 | 2 | R/W | FX Register R12 | Loop counter |
| 0x00301A | 2 | R/W | FX Register R13 | Loop point address |
| 0x00301C | 2 | R/W | FX Register R14 | Rom Address for Getb, Getbh, Getbl, Getbs |
| 0x00301E | 2 | R/W | FX Register R15 | Program Counter |
|
0x003020- 0x00302F | 16 | R/W | Unused | |
| 0x003030 | 2 | R/W | Status flag register | 1 Z Zero flag 2 CY Carry flag 3 S Sign flag 4 OV Overflow flag 5 G Go flag (set to 1 when the GSU is running) 6 R Set to 1 when reading ROM using R14 address 8 ALT1 Mode set-up flag for the next instruction 9 ALT2 Mode set-up flag for the next instruction 10 IL Immediate lower 8-bit flag 11 IH Immediate higher 8-bit flag 12 B Set to 1 when the WITH instruction is executed 15 IRQ Set to 1 when GSU caused an interrupt Set to 0 when read by 658c16 |
| 0x003032 | 1 | R/W | Unused | |
| 0x003033 | 1 | R/W | BRAMR | Backup RAM register |
| 0x003034 | 1 | R/W | PBR | Program bank register |
| 0x003035 | 1 | R/W | Unused | |
| 0x003036 | 1 | ROMBR | Rom bank register | |
| 0x003037 | 1 | R/W | CFGR |
Control flags register
|
| 0x003038 | 1 | R/W | SCBR | Screen base register |
| 0x003039 | 1 | R/W | CLSR |
Clock speed register. 0 = 10.7MHz, 1 = 21.4MHz |
| 0x00303A | 1 | R/W | SCMR |
Screen mode register 0 MD0 color depth mode bit 0 RON = 0 SNES CPU has ROM access |
| 0x00303B | 1 | R | VCR | Version code register |
| 0x00303C | 1 | R/W | RAMBR |
Ram bank register 0 = disabled |
| 0x00303D | 1 | R/W | unused | |
| 0x00303E | 2 | R/W | CBR |
Cache base register 15-4 Specify base address for data to cache from ROM or RAM |
|
0x003040- 0x0030FF | 192 | R/W | Unused | |
|
0x003100- 0x0032FF | 512 | ? | CACHERAM | GSU cache memory |
